1. Field of the Invention
The present invention relates to a clock rate adjustment apparatus and a method for adjusting a clock rate of a clock for an optical storage system; in particular, relates to a clock rate adjustment apparatus and a method adjusting a clock rate according to an indicatory signal retrieved from the optical storage system.
2. Descriptions of the Related Art
Most of electronic systems, such as an optical storage system, need a clock generator to generate some clocks at certain clock rates in order to harmonize or control the operations thereof. Generally speaking, the conventional clock generator may generate a plurality of clocks at different but fixed clock rates. One of the fixed clock rates is selected based on a required operating speed of the electronic systems. Though the conventional clock generator generates clocks at different clock rates to meet the practical needs of the electronic systems, the conventional clock generator still has some drawbacks.
FIG. 1 shows one of the drawbacks, wherein the X axis denotes the processing speeds of an electronic system, and the Y axis denotes clock rates. Lines 11 and 13 represent the two fixed clock rates available for the electronic system. A curve 15 represents the required minimum clock rate under different processing speeds. One can easily observe that the higher the processing speed is, the higher a clock rate is required. A first fixed clock rate, i.e., the line 11 is used when the processing speed is slower than point A because the first fixed clock rate is larger than the required minimum clock rate so it is sufficient to maintain the operation of the electronic system. Once the processing speed exceeds point A, a second fixed clock rate, i.e., the line 13 is used instead because the first fixed clock rate is insufficient to maintain the operation but the second fixed clock rate may. When the processing speed is slightly higher than point A, the electronic system is forced to select the second fixed clock rate which is, however, much larger than the required minimum clock rate. Therefore, such few choices of the clock rates cause unnecessary power consumption.
Due to the aforementioned drawback, a new clock rate adjustment apparatus which may dynamically generate a clock rate based on a required minimum clock rate with a feedback circuit to save power is urgently desired.